The present invention relates to a method and/or architecture for refreshing a memory generally and, more particularly, to a method and/or architecture for refreshing a 1T memory proportional to temperature.
Data (e.g. , a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d) is stored in a 1T memory cell as a voltage level. A xe2x80x9c1xe2x80x9d is stored as a high voltage level which can decrease due to leakage. A xe2x80x9c0xe2x80x9d is stored as a voltage level of zero volts which can increase due to leakage. The 1T memory cell requires a periodic refresh to maintain the voltage level stored in the cell. In many applications, a memory chip uses a ring oscillator to control when the refreshes occur. The frequency of a signal generated by a typical ring oscillator decreases with increasing temperature because of CMOS device characteristics. However, the memory cell leakage increases with temperature. As the temperature increases, refresh using a conventional oscillator can occur less frequently than necessary to maintain the voltage level stored in the memory cell. Thus, the oscillator needs to be designed to support the high temperature refresh rate at the expense of more current.
One method of providing more frequent refreshing is to use a proportional to temperature voltage or current to control the frequency of the refresh oscillator. As the temperature increases, the voltage increases which increases the frequency of the oscillator and the refresh happens more often. For example, a proportional to absolute temperature (PTAT) voltage reference can be used to control a current starved inverter ring oscillator to generate a clock that is proportional to temperature.
One problem with using a PTAT voltage reference is that for low supply voltages (e.g.,  less than 1.8V) typical PTAT generators do not operate. Thus, the design must use more complicated low voltage reference generators. Another downside to using the above approach is that the refresh rate is based upon the cell leakage and the refresh rate, which cannot be matched well, is only approximated by a PTAT generator. A memory refresh operation controlled in response to the leakage of the memory cells would be desirable.
The present invention concerns an apparatus comprising an array of memory cells, a refresh circuit, a first monitor cell, a second monitor cell, and a control circuit. The refresh circuit may be configured to refresh the array of memory cells in response to a refresh control signal. The first monitor cell may be configured to have a charge leakage similar to the memory cells. The second monitor cell may be configured to have a discharge leakage similar to the memory cells. The control circuit may be configured to generate the refresh control signal in response to either a voltage level of the first monitor cell rising above a first pre-determined threshold level or a voltage level of the second monitor cell dropping below a second pre-determined threshold level, where the first and second threshold levels are different.
The objects, features and advantages of the present invention include providing a method and/or architecture for refreshing a memory proportional to temperature that may (i) use pairs of memory cells to determine when a refresh occurs, (ii) use one memory cell that stores a xe2x80x9c1xe2x80x9d and monitors any discharge leakage, (iii) use one memory cell that stores a xe2x80x9c0xe2x80x9d and monitors any charging leakage, (iv) use an array of memory cells to monitor when the refresh occurs for memory redundancy and for weaker cells and/or (v) operate with supply voltages below 1.8V.